An operation processing device such as a central processing unit (CPU) includes a cache memory (also called a cache) that may be accessed at a higher speed than a main storage device. The cache memory is arranged between a processor core, such as a CPU core that is an operation processing section, and the main storage device and retains a part of data stored in the main storage device.
In the case of the cache memory having a hierarchical structure, the operation processing device, for example, includes a second-level cache memory and a first-level cache memory that may be accessed at a higher speed than the second-level cache memory. Hereinafter, the first-level cache memory and the second-level cache memory may be respectively referred to as a primary cache memory and a secondary cache memory.
The secondary cache memory, in the case of access target data not being retained in the primary cache memory (in the case of a cache miss occurring in the primary cache memory), is accessed by the primary cache memory. For example, the primary cache memory outputs a read request to the secondary cache memory in the case of occurrence of a cache miss.
The secondary cache memory, in the case of retaining requested data requested with the read request (in the case of a cache hit occurring in the secondary cache memory), transfers the requested data to the processor core through the primary cache memory. The secondary cache memory, in the case of not retaining the requested data (in the case of a cache miss occurring in the secondary cache memory), acquires the requested data from the main storage device and transfers the acquired requested data to the processor core through the primary cache memory. The secondary cache memory retains the requested data acquired from the main storage device. Accordingly, the requested data that is requested with the read request from the primary cache memory is registered in the secondary cache memory.
The secondary cache memory, in the case of a storage areas that stores the requested data acquired from the main storage device not having a space, executes a replacement process of evicting any data retained in the secondary cache memory from the storage area. Hereinafter, the data that is evicted from the secondary cache memory by the replacement process may be referred to as eviction target data. For example, the secondary cache memory selects data having the longest time of not being accessed as the eviction target data. Suggested as a method for selecting the eviction target data is a method of preferentially selecting data not retained in the primary cache memory as the eviction target data (refer to, for example, Japanese National Publication of International Patent Application No. 2009-524137 and Japanese Laid-open Patent Publication No. 10-105463).
The secondary cache memory includes a processing section that executes a process based on a process request such as a read request. This type of secondary cache memory, in the case of, for example, occurrence of a cache miss, issues a request for the replacement process (hereinafter, may be referred to as a replacement request) in the secondary cache memory and inputs the request into the processing section. The processing section that receives the replacement request executes the replacement process. In this case, for one read request from the primary cache memory, the processing section in the secondary cache memory receives not only the read request but also a plurality of process requests such as a replacement request. For example, the throughput of a series of processes executed in correspondence with one read request from the primary cache memory is decreased along with an increase in the number of process requests received by the processing section in the secondary cache memory. That is, the throughput of a cache memory is decreased along with an increase in the number of process requests issued for the processing section in the secondary cache memory.